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| Offering flexible and cost effective semiconductor fabrication solutions through the utilization of leading CMOS, Embedded flash, Analog and Mixed Signal, RF and BCD process technologies, SSMC has gained recognition from its global customers for consistently delivering semiconductor wafers of high quality and reliability
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| Job No:
171
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CIC: |
Ken Lim
(Reg. No: R1546153) |
| Tapeout Engineering Senior / Principal Engineer |
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EA License No: |
07C3481 |
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Date Posted: |
2015-10-08 |
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| Competencies |
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Minimum Bachelor Degree in Electrical and Electronics or MicroElectronics Engineering.
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Minimum 5 years of relevant experience in wafer fabrication or IC design environment.
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Preferably with knowledge of semiconductor and Microelectronics process workflow.
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Expertise in Shell, Perl or TCL scripting is a must.
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Knowledge in UNIX/LINUX commands is required.
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Familiar with Cadence Virtuoso, MySQL client program is preferred.
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Able to work as a team and multi-task.
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Passion to learn new skills.
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Driven, motivated, takes initiative and meticulous.
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| ResponsibiliTies |
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To work closely with Technology Development team, Process integration team and Product Engineering team to resolve customers’ design issues and improve the product yield.
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To work with Tapeout Operation team to develop automation scripts (Perl, TCL, and Shell) and systems to streamline tapeout processes.
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Responsible for automation script documentation and management.
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To handle development and engineering tapeouts which require non-standard frame and prime die data handling while establishing a production friendly way of working for Operation team after development phase.
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To train the Tapeout Operation team competency on the script architecture and operation.
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To lead productivity projects and ensure project closure according to project timeline.
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To deliver value added services to customers through DFM, yield enhancement projects and engineering requests activities.
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Familiar with Cadence MaskCompose for frame data preparation.
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Familiar with Synopsys MBOPC, Synopsys CATS and Cadence PVS for prime-die OPC and booleans.
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| Experience |
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Minimum Bachelor Degree in Electrical and Electronics or MicroElectronics Engineering.
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Minimum 5 years of relevant experience in wafer fabrication or IC design environment.
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Preferably with knowledge of semiconductor and Microelectronics process workflow.
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Expertise in Shell, Perl or TCL scripting is a must.
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Knowledge in UNIX/LINUX commands is required.
-
Familiar with Cadence Virtuoso, MySQL client program is preferred.
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Able to work as a team and multi-task.
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Passion to learn new skills.
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Driven, motivated, takes initiative and meticulous.
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| Salary |
| $5000 -- $6500 per Month |
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QUICK APPLY |
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We will try our best to reply all candidates within 7 working days.
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